? semiconductor components industries, llc, 2006 july, 2006 ? rev. 4 1 publication order number: MTD6N15/d MTD6N15 power field effect transistor dpak for surface mount n?channel enhancement?mode silicon gate this tmos power fet is designed for high speed, low loss power switching applications such as switching regulators, converters, solenoid and relay drivers. features ? silicon gate for fast switching speeds ? low r ds(on) ? 0.3 max ? rugged ? soa is power dissipation limited ? source?to?drain diode characterized for use with inductive loads ? low drive requirement ? v gs(th) = 4.0 v max ? surface mount package on 16 mm tape ? pb?free package is available maximum ratings rating symbol value unit drain?source voltage v dss 150 vdc drain?gate voltage (r gs = 1.0 m ) v dgr 150 vdc gate?source voltage ? continuous ? non?repetitive (t p 50 s) v gs v gsm 20 40 vdc vpk drain current ? continuous drain current ? pulsed i d i dm 6.0 20 adc total power dissipation @ t c = 25 c derate above 25 c p d 20 0.16 w w/ c total power dissipation @ t a = 25 c derate above 25 c (note 1) p d 1.25 0.01 w w/ c total power dissipation @ t a = 25 c (note 1) derate above 25 c (note 2) p d 1.75 0.014 w w/ c operating and storage junction temperature range t j , t stg ?65 to +150 c thermal characteristics characteristic symbol value unit thermal resistance ? junction?to?case ? junction?to?ambient (note 1) ? junction?to?ambient (note 2) r jc r ja r ja 6.25 100 71.4 c/w stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. when surface mounted to an fr4 board using the minimum recommended pad size. 2. when surface mounted to an fr4 board using 0.5 sq. in. drain pad size. http://onsemi.com device package shipping ? ordering information marking diagram & pin assignments y = year ww = work week 6n15 = device code g = pb?free package case 369c dpak (surface mount) style 2 d s g yww t 6n15g MTD6N15t4 dpak 2500/tape & ree l 4 drain 3 source 1 gate 2 drain n?channel 1 2 3 4 150 v 0.3 r ds(on) max 6.0 a i d max v (br)dss ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. MTD6N15t4g dpak (pb?free) 2500/tape & ree l
MTD6N15 http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min max unit off characteristics drain?source breakdown voltage (v gs = 0 vdc, i d = 0.25 madc) v (br)dss 150 ? vdc zero gate voltage drain current (v ds = rated v dss , v gs = 0 vdc) t j = 125 c i dss ? ? 10 100 adc gate?body leakage current, forward (v gsf = 20 vdc, v ds = 0) i gssf ? 100 nadc gate?body leakage current, reverse (v gsr = 20 vdc, v ds = 0) i gssr ? 100 nadc on characteristics (note 3) gate threshold voltage (v ds = v gs , i d = 1.0 madc) t j = 100 c v gs(th) 2.0 1.5 4.5 4.0 vdc static drain?source on?resistance (v gs = 10 vdc, i d = 3.0 adc) r ds(on) ? 0.3 drain?source on?voltage (v gs = 10 vdc) (i d = 6.0 adc) (i d = 3.0 adc, t j = 100 c) v ds(on) ? ? 1.8 1.5 vdc forward transconductance (v ds = 15 vdc, i d = 3.0 adc) g fs 2.5 ? mhos dynamic characteristics input capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz) (see figure 11) c iss ? 1200 pf output capacitance c oss ? 500 reverse transfer capacitance c rss ? 120 switching characteristics* (t j = 100 c) turn?on delay time (v dd = 25 vdc, i d = 3.0 adc, r g = 50 ) (see figures 13 and 14) t d(on) ? 50 ns rise time t r ? 180 turn?off delay time t d(off) ? 200 fall time t f ? 100 total gate charge (v ds = 0.8 rated v dss , i d = rated i d , v gs = 10 vdc) (see figure 12) q g 15 (typ) 30 nc gate?source charge q gs 8.0 (typ) ? gate?drain charge q gd 7.0 (typ) ? source?drain diode characteristics* forward on?voltage (i s = 6.0 adc, di/dt = 25 a/ s, v gs = 0 vdc) v sd 1.3 (typ) 2.0 vdc forward turn?on time t on limited by stray inductance reverse recovery time t rr 325 (typ) ? ns 3. pulse test: pulse width 300 s, duty cycle 2%. t, temperature ( c) figure 1. power derating p d , power dissipation (watts) 25 20 15 10 5 0 150 125 100 75 50 25 2.5 2 1.5 1 0.5 0 t a t c t c
MTD6N15 http://onsemi.com 3 typical electrical characteristics 2 1.6 1.2 0.8 0.4 0 v ds , drain?to?source voltage (volts) figure 2. on?region characteristics i d , drain current (amps) t j = 25 c 24 20 16 12 8 4 0 60 50 40 30 20 10 0 10 v 9 v 8 v 7 v 6 v 5 v v ds = v gs i d = 1 ma ? 50 0 50 100 150 t j , junction temperature ( c) figure 3. gate?threshold voltage variation with temperature v gs(th) , gate threshold voltage (volts) 3.6 3.2 2.8 2.4 2 i d , drain current (amps) v gs , gate?to?source voltage (volts) figure 4. transfer characteristics v ds = 10 v t j = 25 c ?55 c 100 c 14 12 10 8 6 4 2 0 46810 2 1.6 1.2 0.8 0.4 0 ? 50 0 50 100 150 200 t j , junction temperature ( c) figure 5. breakdown voltage variation with temperature v (br)dss , drain?to?source breakdown voltage (normalized) v gs = 0 v i d = 0.25 ma r ds(on) , drain?to?source resistance (ohms) i d , drain current (amps) figure 6. on?resistance versus drain current v gs = 10 v 0.30 0.25 0.20 0.15 0.10 0.05 0 20 16 12 8 4 0 t j = 100 c 25 c ?55 c r ds(on) , drain?to?source resistance (normalized) t j , junction temperature ( c) figure 7. on?resistance variation with temperature v gs = 10 v i d = 3 a ? 50 0 50 100 150 200
MTD6N15 http://onsemi.com 4 safe operating area v ds , drain?to?source voltage (volts) figure 8. maximum rated forward biased safe operating area v ds , drain?to?source voltage (volts) figure 9. maximum rated switching safe operating area i d , drain current (amps) r ds(on) limit thermal limit package limit i d , drain current (amps) t j 150 c 20 10 5 2 1 0.5 0.2 0.1 0.05 0.03 300 200 100 70 50 30 20 10 7 5 3 2 1 0.3 0.5 0.7 10 s 1 ms 10 ms dc 100 s t c = 25 c v gs = 20 v single pulse 20 15 10 5 0 0 20 40 60 80 100 120 140 160 forward biased safe operating area the fbsoa curves define the maximum drain?to?source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. the curves are based on a case temperature of 25 c and a maximum junction temperature of 150 c. limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. motorola application note, an569, ?transient thermal resistance?general data and its use? provides detailed instructions. switching safe operating area the switching safe operating area (soa) of figure 9 is the boundary that the load line may traverse without incurring damage to the mosfet. the fundamental limits are the peak current, i dm and the breakdown voltage, v (br)dss . the switching soa shown in figure 8 is applicable for both turn?on and turn?off of the devices for switching times less than one microsecond. the power averaged over a complete switching cycle must be less than: t j(max) ? t c r jc t, time or pulse width (ms) figure 10. thermal response r(t), effective transient thermal resistance (normalized) r jc (t) = r(t) r jc r jc (t) = 6.25 c/w max d curves apply for power pulse train shown read time at t 1 t j(pk) ? t c = p (pk) r jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 1000 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1 2 3 5 10 20 50 100 200 500 0.01 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.5 0.7 d = 0.5 0.2 0.1 0.05 0.02 0.01 single pulse
MTD6N15 http://onsemi.com 5 c rss gate?to?source or drain?t o?source voltage (volts) figure 11. capacitance variation c, capacitance (pf) v gs v ds v ds = 0 0 2000 1600 1200 25 20 10 0 5 10 figure 12. gate charge versus gate?to?source voltage q g , total gate charge (nc) 16 0 08 12 8 4 12 16 20 515 400 v ds = 50 v v gs , gate source voltage (volts) t j = 25 c i d = 6 a 75 v 120 v t j = 25 c v gs = 0 4 800 15 30 35 c iss c oss resistive switching pulse generator v dd v out v in r gen 50 z = 50 50 dut r l figure 13. switching test circuit t off output, v out inverted t on t r t d(off) t f t d(on) 90% 90% 10% input, v in 10% 50% 90% 50% pulse width figure 14. switching waveforms
MTD6N15 http://onsemi.com 6 package dimensions dpak case 369c?01 issue o d a k b r v s f l g 2 pl m 0.13 (0.005) t e c u j h ?t? seating plane z dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.180 bsc 4.58 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.090 bsc 2.29 bsc r 0.180 0.215 4.57 5.45 s 0.025 0.040 0.63 1.01 u 0.020 ??? 0.51 ??? v 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? 123 4 style 2: pin 1. gate 2. drain 3. source 4. drain 5.80 0.228 2.58 0.101 1.6 0.063 6.20 0.244 3.0 0.118 6.172 0.243 mm inches scale 3:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5773?3850 MTD6N15/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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